This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-336059, filed Nov. 26, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, a semiconductor device employing a strained-Si layer as an active region and a method of manufacturing the same.
The performance of Si semiconductor elements, in particular, MOSFETs, has increased year after year with the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit, and that a carrier mobility has almost reached theoretical mobility in Si. Under the circumstances, it is difficult to further improve the performance of MOSFETs.
To attain higher performance of the semiconductor device, attempts have been made to use a crystal such as a GaAs semiconductor crystal or an SiC semiconductor crystal in place of an Si crystal since they have a faster theoretical mobility than the Si crystal.
However, it is difficult to introduce the manufacturing process for the GaAs semiconductor crystal or the SiC crystal into the manufacturing process of the Si device presently used. Therefore, a lot of time and labor are required for developing this kind of device. As a matter of fact, when this kind of device is manufactured on a large scale, the whole manufacturing line must be redesigned from the beginning or some of the manufacturing apparatus must be replaced.
Therefore, it is now strongly desired that a high-performance Si-based semiconductor device is developed in a short development period and at a low cost by using know-how of the presently-used manufacturing process and manufacturing apparatus for the Si device.
To attain such a device, studies have been made to improve the performance of Si-MOSFET by increasing the electron mobility in Si. As one of the methods for increasing the electron mobility in Si, a technique for applying a strain to a Si layer has drawn attention. Generally, when the strain is applied to a semiconductor layer, the band structure is changed to suppress the scattering of carriers in a channel. Therefore, the electron mobility is expected to improve.
To explain more specifically, when a compound crystal layer including a material having a lattice constant larger than that of Si is formed on a Si substrate, for example, a SiGe compound crystal containing 20 atomic % of Ge (hereinafter, simply referred to as xe2x80x9cSiGe layerxe2x80x9d) is formed as thick as several xcexcm so as to obtain lattice relaxation, and then, a Si layer as thin as several nm is formed on the lattice-relaxed SiGe layer thus obtained, strain, which is generated due to the difference in lattice constant between SiGe and Si, is applied to the Si layer. As a result, a strained Si layer is obtained.
It has been reported that if the strained Si layer thus obtained is employed as a channel of a MOSFET, the electron mobility can be greatly improved to about 1.76 times larger than that of the non-strained Si layer (J. Welser, J. L. Hoyl, S. Tagkagi and J. F. Gibbons, IEDM 94-373).
Furthermore, another method is known for improving the electron mobility in Si by reducing the channel length of the MOSFET. However, when the channel length is reduced, the effect of stray capacitance increases, with the result that it is difficult to improve the electron mobility as desired.
To overcome this problem, attention is drawn to a structure having a channel layer formed within an SOI layer (Silicon On Insulator: an Si layer is formed on an Si substrate with an insulating film interposed between them). Since the channel layer is completely isolated by the insulating film in this structure, it becomes easier to decrease the stray capacitance and isolate the element. Furthermore, reduction of power consumption and higher integration can be expected.
Under the circumstances, attempts have been made to form a structure of a semiconductor device by employing the strained Si layer (for improving the electron mobility) in the SOI structure (responsible for lowering the stray capacitance and attaining element isolation).
The structure of such a semiconductor device will be explained with reference to FIGS. 1A and 1B.
As shown in FIG. 1A, an SOI substrate having an SiO2 insulating film 2 and SOI layer 3 having a thickness between 20 nm and 30 nm previously formed on an Si substrate 1 is prepared. Thereafter, an SiGe layer 4 containing 20 atomic % of Ge and having a larger lattice constant than Si is formed on the SOI substrate. The SiGe layer herein is formed sufficiently thicker than the SOI layer 3.
Then, as shown in FIG. 1B, annealing is performed for one hour at 1100xc2x0 C. in a nitrogen containing atmosphere. At this time, since tensile strain is applied from the SiGe layer 4 to the SOI layer 3, the SOI layer 3 is plastically deformed and thus lattice-relaxed. At the same time, the SOI layer 4 is also lattice-relaxed. By the plastic deformation, a dislocation 33 such as a threading dislocation and a misfit dislocation, is produced in the SOI layer 3.
Subsequently, a thin Si film is formed on the lattice-relaxed SiGe layer 4. Due to the presence of the thin Si film, it is possible to form a strained Si layer 5 having a tensile strain.
Since the dislocation is produced and confined within the lattice-relaxed SOI layer 3, it has been considered that the most of dislocation 33 is not propagated to the lattice-relaxed SiGe layer 4. However, it was found that if annealing for lattice relaxation is performed in a nitrogen-containing atmosphere for one hour at a temperature of 1100xc2x0 C., the dislocation 33 can be propagated to the surface of SiGe layer 4 with a density of about one/10 xcexcm2. Due to defects such as a dislocation, the crystallinity of the strained Si layer 5 deteriorates. Thereafter, a semiconductor device such as a MOSFET is formed on the strained Si layer 5. However, the deterioration in crystallinity of the strained Si layer 5 may degrade characteristics of the resultant semiconductor device. The deterioration more significantly appears with the miniaturization of the semiconductor device.
The defects produced by lattice-relaxation of the SiGe layer 4 may be sometimes amplified in a high-temperature processing step when a gate and an electrode are formed and when annealing is performed for recovering the crystallinity after ion doping. In this case, the crystallinity of the strained Si layer 5 may be further degraded.
To prevent the dislocation 33, which is produced in the SOI layer for lattice-relaxation, from propagating to the surface of the SiGe layer, the SiGe layer 4 must be formed with a thickness of several xcexcm or more. However, to produce a sufficient effect of suppressing the stray capacitance due to the SOI substrate structure, it is necessary to suppress a total thickness from the SiO2 insulating layer 2 to the strained Si layer 5 (serving as a channel layer) as much as possible. However, since, in this method, the SiGe layer 4 must be formed with several xcexcm, it is impossible to sufficiently produce the effect brought about by the SOI substrate structure.
As described above, there are problems in a conventional semiconductor device having a strained Si layer (as a channel layer) formed on the SOI substrate. That is, to prevent the defects, the semiconductor film has to be formed thick on the SOI substrate insulating film. If the thickness of the semiconductor layer formed on the SOI substrate insulting film is reduced, the defects become clearly apparent.
An object of the present invention is to provide a high-performance semiconductor device and a method of the manufacturing the high-performance semiconductor device capable of not only reducing the thickness of a film formed on an insulating layer of an SOI substrate but also decreasing defects of a strained layer serving as a channel layer, and capable of applying sufficient strain to the channel layer.
To attain the aforementioned object, a semiconductor device according to a first aspect of the present invention comprises:
a substrate;
an insulating film formed on the substrate;
a first semiconductor layer lattice-relaxed and formed on the insulating film substantially in contact therewith;
a second semiconductor layer having a tensile lattice strain and formed on the first semiconductor layer, a lattice constant of the second semiconductor layer being smaller than that of the first semiconductor layer;
a gate insulting layer selectively formed on the second semiconductor layer;
a gate electrode formed on the gate insulating film;
a channel region formed in a surface of the second semiconductor layer immediately under the gate electrode; and
a pair of source/drain regions selectively formed in the second semiconductor layer so as to be spaced apart from each other by the channel region.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising:
a first step of forming an insulating film on a substrate;
a second step of forming a stacked substrate having a stacked layer of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer;
a third step of bonding the substrate and the stacked substrate such that the insulating film faces the first semiconductor layer;
a fourth step of removing the stacked substrate so as to allow the first semiconductor layer and at least part of the second semiconductor layer to remain, thereby forming a stacked structure formed of the first semiconductor layer lattice-relaxed and the second semiconductor layer having a strain applied on a surface thereof; and
a fifth step of forming a transistor on the semiconductor layer having the strain applied on the surface thereof.
According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising:
a first step of forming an insulating film on a surface of a substrate;
a second step of forming a first semiconductor layer on a surface of a semiconductor substrate;
a third step of bonding the substrate and the semiconductor substrate such that the insulating film faces the first semiconductor layer;
a fourth step of removing the semiconductor substrate so as to allow at least the first semiconductor layer to remain, thereby lattice-relaxing the first semiconductor layer;
a fifth step of stacking a second semiconductor layer on the first semiconductor layer, thereby applying a tensile strain to the second semiconductor layer;
a sixth step of forming a transistor on the second semiconductor layer;
In the present invention, the following constitutions are preferable.
(1) The thickness of the first semiconductor layer is 80 nm or less.
(2) The total thickness of the first semiconductor layer and the second semiconductor layer is 100 nm or less.
(3) The lattice distance of the first semiconductor layer is nonuniform in a thickness direction.
(4) The first semiconductor layer is an SiGe layer, the Ge content of at least the surface of the first semiconductor layer in contact with the second semiconductor layer is larger than 30 atomic %, and a second semiconductor layer is Si.
(5) The first semiconductor layer is an SiGe layer, having a gradient content such that the Ge content of the first semiconductor layer at a portion thereof adjacent to the base substrate is 30 atomic % or less and the Ge content of the first semiconductor layer at a portion thereof adjacent to the second semiconductor layer is larger than 30 atomic %, and the second semiconductor layer is Si.
(6) The first semiconductor layer and the second semiconductor layer are different in lattice constant and a combination selected from the group consisting of Si, SiGe, GaAs, SiC, GaN, GaAlAs, InGaP, InGaPAs, Al2O3 BN, BNC, C, doped Si, SiNx and ZnSe, to produce a tensile strain in the second semiconductor layer. More specifically, the second semiconductor layer or the semiconductor substrate is Si, B, As, P, C, Ge, Ga, In, Al, Zn, Se or a compound crystal thereof. Furthermore, the second substrate is any one of Si, GaAs, ZnSe, SiC, Ge, SiGe, sapphire, organic glass, inorganic glass, and plastic.
Note that a covalent radius of Si and Ge is 1.17 and 1.22, respectively. When an SiGe layer and an Si layer are stacked on an Si substrate in this order by a general epitaxial growth technique, the lattice of an SiGe layer 4xe2x80x2 matches with the lattices of upper and lower Si layers 3, 5xe2x80x2 and deforms longitudinally, as shown in FIG. 2A and a tensile strain is generated in the SiGe layer 4xe2x80x2 in a longitudinal direction of the figure. To an Si layer formed on such an SiGe layer 4xe2x80x3, a sufficient tensile strain is not applied.
On the other hand, there is known another technique (e.g., Japanese Patent Application KOKAI No. 11-121377) characterized by doping B (boron) into the SiGe etching stopper layer in an amount of 1020-1021 atoms/cm3 by making use of its covalent-bonding radius of 0.88. The technique teaches omission of CMP (chemical Mechanical Polishing) to be performed after cleaving in a hydrogen delamination method performed at the time the SOI substrate is formed. FIG. 2B schematically shows how to perform lattice matching in this technique. Reference numerals 3 and 5xe2x80x2 denote Si. Reference numeral 4xe2x80x3 denotes B-doped SiGe. The B-doped SiGe layer 4xe2x80x3 is used as an etching stopper, which is removed later. In the aforementioned publication, an SiGe layer can be formed in place of the uppermost Si layer 5xe2x80x2 and later used as a device layer. However, since the SiGe layer contains B which is heat-diffused from the SiGe (B) layer 4xe2x80x3 in a manufacturing process, it inevitably has a residual compression strain. It is possible to further form an Si layer (serving as a device layer) on the SiGe device layer. However, sufficient strain is not applied to the Si layer.
The stained Si layer serving as the device layer is attained by forming a three-layered structure of Si/SiGe/Si as shown in FIGS. 1A and 1B. However, a dislocation 33 is propagated to a Si layer 5, as aforementioned. In the present invention, as shown in FIG. 2C, a lattice-relaxed SiGe layer 4 is formed on a silicon oxide film 2 substantially in contact therewith, and thereafter, the Si layer 5 is formed on the lattice-relaxed SiGe layer 4 by a bonding method etc. At this time, a sufficient tensile strain is generated in the Si layer 5 in the lateral direction in the figure by the lattice-relaxed SiGe layer. Furthermore, the crystallinity of the strained Si layer 5 is not degraded, because the SOI layer 3 having the dislocations 33 is not provided thereunder. In the present invention, a high-temperature annealing step is not employed to lattice-relax the SiGe layer unlike a conventional technique. Therefore, the present invention is free from such a phenomenon that a threading dislocation due to high temperature annealing is introduced in an underlying silicon layer and reaches the strained Si device layer forming a channel to deteriorate device characteristics. Hence, in the present invention, the thickness of the SiGe layer can be reduced than that formed by using the conventional technique, so that the total thickness of the SiGe layer and Si layer on the insulating layer can be reduced to about ⅔ (100 nm or less) of that of conventional one. Accordingly, a sufficient strain can be applied to the semiconductor device layer without losing advantages of the SOI structure, that is, without the effect from the stray capacitance.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.